The present invention is directed, in general, to processing systems and, more specifically, to systems and methods for debugging a highly integrated microprocessor.
The last two decades have seen rapid growth in the power and complexity of microprocessors. At the same time, the price of microprocessors, relative to other technologies and adjusted for inflation, has decreased. As a result, desktop personal computers and other microprocessor-dependent processing systems are affordable to a large segment of the population and are more powerful that some not-very-old mainframe computers.
The greatly increased complexity of microprocessors, however, has its drawbacks. As more and more functions are either expanded in or added to a microprocessor, the ability of a programmer or engineer to debug problems in a microprocessor or problems in software executed by a microprocessor becomes diminished. This happens, in part, because there are a limited number of pins on a microprocessor that can be used to access and examine the internal registers, buses, interfaces, caches, instruction units, functional units, and other components of a microprocessor. For example, reads and writes to an on-chip level one (L1) cache in a microprocessor are not directly observable on an external pin of a microprocessor.
A number of techniques may be used to debug a conventional microprocessor and/or to debug software executed by a microprocessor. One technique involves editing source code to include unique print statements associated with particular program branches in order to determine the paths the program took during execution. Another technique involves using a debugger, which causes a program to execute to some break point and then halt. This allows a programmer to modify memory, to analyze certain registers (such as debug registers) that are accessible in the microprocessor, and to change break points, if necessary. Program execution may then be resumed.
These types of techniques are often effective for debugging software, but are frequently of limited use in debugging microprocessors. This is because many debugging techniques are intrusive enough to perturb the normal operation of the microprocessor, thereby causing a problem to not appear.
Therefore, there is a need in the art for improved techniques for debugging microprocessors. In particular, there is a need for systems and methods for debugging a microprocessor that are minimally intrusive into the normal operation of a highly integrated microprocessor. More particularly, there is a need for systems and methods for accessing and examining selected internal components of a microprocessor without excessively perturbing the normal operation of the microprocessor and without requiring the addition of a large number of external pins.
The limitations inherent in the prior art described above are overcome by the present invention which provides a data processor having improved debugging features that are capable of transferring from the data processor selected ones of instructions, data, and addresses in response to the occurrence of one or more of execution of a branch instruction, detection of a trigger value on an internal bus, or execution of a unique spray instruction.
In one advantageous embodiment of the present invention, the data processor comprises: 1) a plurality of functional units capable of executing sequences of instructions, and 2) a debugging apparatus capable of detecting a change of flow from a first sequence of instructions to a second sequence of instructions. The debugging apparatus, in response to the detection, outputs from the data processor a first address associated with the change of flow.
In one embodiment of the present invention, the at least one of the plurality of functional units is capable of generating a change-of-flow (COF) signal when the change of flow occurs in the at least one functional unit.
In another embodiment of the present invention, the debugging apparatus comprises a register capable of receiving the COF signal and in response to the receipt of the COF signal, storing the first address associated with the change of flow.
In still another embodiment of the present invention, the register is a serial shift register capable of serially shifting the stored first address from the data processor.
In yet another embodiment of the present invention, the first address associated with the change of flow is an address associated with one of the second sequence of instructions.
In a further embodiment of the present invention, the debugging apparatus is further capable of determining that a conditional branch instruction executed by one of the plurality of functional units has not caused a change of flow.
In a still further embodiment of the present invention, the debugging apparatus, in response to the determination, outputs from the data processor a second address associated with the conditional branch instruction.
In a yet further embodiment of the present invention, the second address is an address of an instruction following the conditional branch instruction.
According to a second advantageous embodiment of the present invention, the data processor comprises: 1) a plurality of functional units capable of executing instructions, 2) a communication bus capable of transferring one or more of addresses, data, instructions, and control bits between the plurality of functional units, and 3) a debugging apparatus capable of detecting at least one of a selected address value, a selected data value, a selected instruction value, and a selected control bits value, and in response to the detection, capturing on the communication bus a selected number of the one or more of addresses, data, instructions, and control bits.
According to one embodiment of the present invention, the debugging apparatus comprises a built-in programmable logic analyzer (PLA) capable of monitoring the communication bus and detecting the at least one of a selected address value, a selected data value, a selected instruction value, and a selected control bits value.
According to another embodiment of the present invention, the programmable logic analyzer is further capable of capturing the selected number of one or more of addresses, data, instructions, and control bits.
According to still another embodiment of the present invention, the debugging apparatus further comprises a memory associated with the programable logic analyzer, wherein the programmable logic analyzer stores in the memory the captured selected number of one or more of addresses, data, instructions, and control bits.
According to yet another embodiment of the present invention, the selected number of one or more of addresses, data, instructions, and control bits captured by the programmable logic analyzer captures is a programmable number modifiable by a user.
According to a further embodiment of the present invention, the debugging apparatus is capable of transferring the captured selected number of the one or more of addresses, data, instructions, and control bits to an external bus associated with the data processor.
According to a still further embodiment of the present invention, the external bus comprises a peripheral component interconnect (PCI) bus.
According to a yet further embodiment of the present invention, the external bus comprises a main memory bus coupling the data processor to a system memory.
According to a third advantageous embodiment of the present invention, there is provided, for use in a data processor, a method of debugging a data processor comprising the steps of: 1) executing a debugging instruction, and 2) in response to the execution of the debugging instruction, outputting from the data processor at least one of an address and a data value associated with at least one instruction following the debugging instruction.
According to another embodiment of the present invention, the step of executing the debugging instruction enables a selected flag in the data processor, wherein the data processor, in response to the enablement of the selected flag, writes the at least one of an address and a date value to a selected output of the data processor.
According to still another embodiment of the present invention, the at least one instruction is the next sequential instruction following the debugging instruction.
According to yet another embodiment of the present invention, the step of executing the debugging instruction comprises the substep of determining that a data value associated with a current instruction matches a debug value stored in a debug register associated with the data processor.
According to yet another embodiment of the present invention, the debugging instruction comprises an opcode having a parity bit enabled.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.